1. Field of the Invention
The present invention relates to a semiconductor circuit, in which power consumption can be reduced, and a semiconductor circuit system using the same.
2. Description of the Related Art
Display apparatuses such as a liquid crystal display apparatus and a plasma display apparatus are widely used. In such a display apparatus, it is desired to reduce power consumption.
FIG. 1 shows the structure of a conventional liquid crystal display apparatus. Referring to FIG. 1, the conventional liquid crystal display apparatus 101 is composed of a display device 102, a vertical drive unit 103 and a horizontal drive unit 104.
The display device 102 is a liquid crystal panel section which is conventionally known. The liquid crystal panel section has X rows of gate bus lines (not shown) extending in a horizontal direction and Y columns of data bus lines (not shown) extending in a vertical direction. A plurality of pixels are provided in areas surrounded by those lines. Each pixel is connected with one gate bus line and one data bus line. Each pixel is composed of a pixel electrode and a switching element such as a field effect transistor. The gate of the switching element is connected with the gate bus line, a source thereof is connected with the data bus line, and a drain thereof is connected with the pixel electrode.
The vertical drive unit 103 has a function to scan the gate bus lines, and the horizontal drive unit 104 has a function to control the voltage level of each of the data bus lines.
Next, an operation of the conventional liquid crystal display apparatus will be described below. The vertical drive unit 103 scans gate bus lines from the top line to the bottom line, and the horizontal drive unit 104 controls the voltage level of the data bus line connected with the pixel based on pixel data. Thus, the pixel which is connected with the gate bus line scanned by the vertical drive unit 103 can display the pixel data.
FIG. 2 shows the structure of the horizontal drive unit 104. Referring to FIG. 2, the horizontal drive unit 104 is composed of a plurality of horizontal drive circuits 111-h (h=1, 2, 3, . . . , n) which are connected with an input terminal 112. When the voltage level of an input signal D101 supplied from the input terminal 112 is high, all the horizontal drive circuits 111-h are driven and activated
FIG. 3 shows the structure of the conventional horizontal drive circuit 111-h. Referring to FIG. 3, the conventional horizontal drive circuit 111 is composed of a first differential input circuit 113, a second differential input circuit 114, a third differential input circuit 118, a first register circuit 115 and a second register circuit 116. Also, the conventional horizontal drive circuit 111-h has a start pulse input terminal 119 to which a start pulse signal is supplied, and a start pulse output terminal 120 to output the start pulse signal. The start pulse signal is used to establish synchronization when the first register circuit 115 and the second register circuit 116 take in data signals D102b and D102c. 
The first differential input circuit 13 is connected with the input terminal 112, clock signal input terminals D102a-1 and D102a-2 and a plurality of flip-flops 115-i (i=1 to j) of the first shift register circuit 115. The first differential input circuit 113 operates when the voltage value of the input terminal 112 is VB (VB>0). The clock signal D102a is supplied to the first differential input circuit 113 from the clock signal input terminals D102a-1 and D102a-2. Also, when the clock signal D102a is supplied, the first differential input circuit 13 supplies the clock signal D102a to the plurality of flip-flops 115-i.
The second differential input circuit 114 is connected with the input terminal 112, data signal input terminals D102b-1 and D102b-2 and first data registers 116a of the second register circuit 116. The first data signal D102b is supplied from the data signal input terminals D102b-1 and D102b-2 to the second differential input circuit 114. The second differential input circuit 114 is activated when the voltage value of the input terminal 112 is VB (VB>0). Also, the second differential input circuit 114 supplies a signal corresponding to the first data signal D102b to the first data registers 116a when the first data signal D102b is supplied.
The third differential input circuit 118 is connected with the input terminal 112, data signal input terminals D102c-1 and D102c-2 and the second data registers 116b of the second register circuit 116. The third differential input circuit 118 is activated when the voltage value of the input terminal 112 is VB (VB>0). The second data signal D102c is supplied to the third differential input circuit 113 from the data signal input terminals D102c-1 and D102c-2. Also, the third differential input circuit 118 supplies the second data signal D102c to the second data registers 116b when the second data signal D102c is supplied.
The first register circuit 115 is connected with the first differential input circuit 113, the start pulse input terminal 119 and the start pulse output terminal 120.
The first register circuit 115 is composed of the plurality of flip-flops 115-i. Also, the flip-flops 115-i are connected with the first differential input circuit 113. Moreover, each of the flip-flops 115 is connected with a corresponding one of sets of a first data register 116a and a second data register 116b in the second register circuit 116. The plurality of flip-flops 115-i are cascade-connected to form a shift register, and delays the start pulse signal one clock by one clock. The start pulse input terminal 119 is connected with the flip-flop 115-1 as the first end of this cascade connection, and the start pulse output terminal 120 is connected with the flip-flop 115-(j−1).
Next, the operation of the plurality of flip-flops 115-i will be described below.
First, the start pulse signal is supplied from the start pulse input terminal 119 to the flip-flop 115-1. Then, the clock signal D102a is supplied from the first differential input circuit 113 to each of the flip-flops 115-i. When the start pulse signal is supplied, the flip-flop 115-1 generates one pulse signal in response to the rising edge of the clock signal D102a and supplies the pulse signal to the corresponding set of the first data register 16a and the second data register 116b. Then, the flip-flop 115-1 outputs a shift signal to the flip-flop 115-2 as a next flip-flop before a next pulse of the clock signal D102a rises up.
Also, when the shift signal is supplied from the flip-flop 115-(p−1) (p is an integer to satisfy 2≦p≦=j−1), the flip-flop 115-p generates one pulse signal, and supplies the pulse signal to the corresponding set of the first data register 116a and the second data registers 116b. Then, the flip-flop 115-p outputs a shift signal to the flip-flop 115-(p+1) before a next pulse of the clock signal D102a rises up.
Also, when a shift signal is supplied from the flip-flop 115-(j−2), the flip-flop 115-(j−1) generates one pulse signal, and supplies the pulse signal to the corresponding set of the first data register 116a and the second data register 116b. Also, the flip-flop 115-(j−1) outputs a shift signal to the flip-flop 115-j and the start pulse output terminal 120 before a next pulse of the clock signal D102a rises up.
In addition, when a shift signal is supplied from flip-flop 115-(j−1), the flip-flop 115-j generates one pulse signal, and supplies the pulse signal to the corresponding set of the first data register 116a and the second data register 116b which are connected with the flip-flop 115-j.
The second register circuit 116 is connected with the second differential input circuit 114, the third differential input circuit 118 and the first register circuit 115. The second register circuit 116 is composed of register sections 116c for the same number as the number of flip-flops 115-i. Here, each of the register sections 116c is composed of the first data register 116a and the second data register 116b. The respective register sections 116c are connected with the flip-flops 115-i, respectively.
Next, an operation of each register section 116c will be described below. First, the pulse signal is supplied from the flip-flop 115-i to a corresponding one of the register sections 116c, respectively. The first data register 116a in the corresponding register section 116c latches a signal corresponding to the first data signal D102b supplied from the second differential input circuit 114 at the timing of the pulse signal supplied from the corresponding flip-flop 115-i. Also, the second data register 116b in the corresponding register section 116c latches a signal corresponding to the second data signal D102c supplied from the third differential input circuit 118 at the same timing.
Next, an operation of the horizontal drive circuit 111 will be described below. The start pulse signal is supplied from the start pulse input terminal 119 and is delayed by the flip-flops 115-i as the shift register in response to the edge of the clock signal D102a outputted from the first differential input circuit 113. The data signal corresponding to the data signal D102b is outputted from the second differential input circuit 114 in synchronous with the clock signal D102a. Each data register 116a latches the data signal at the timing of the rising edge of the pulse signal from the flip-flop 115-i.
As described above, when the conventional horizontal drive unit 104 operates, all the horizontal drive circuits 111-h are driven. Also, all the differential input circuits 113, 114 and 118 of the horizontal drive circuit 111-i are activated.
Here, in the conventional horizontal drive circuit, each of the differential input circuits 113, 114 and 118 requires the time of about 500 nanoseconds for a stable operation after the differential input circuit is activated. Also, the time of about 300 nanoseconds is needed to latch the data signals D102b and D102c. For this reasons, in the conventional liquid crystal display apparatus, all the horizontal drive circuits 111-h are driven at the same time for the stable operation of the horizontal drive unit.
In conjunction with the above description, a semiconductor integrated circuit is disclosed in Japanese Laid Open Patent application (JP-A-Heisei 9-27192). In this reference, the semiconductor integrated circuit is composed of an input/output interface which inputs and outputs a signal having a smaller amplitude voltage than a power supply voltage in synchronous with a clock signal. A first input circuit of the input/output interface receives an external clock signal and is composed of differential MOSFETs having a gate to which the small amplitude signal and a reference voltage having a level of a half of the small amplitude, and a current source MOSFET connected to common sources of the differential MOSFETs and operating in an ordinary state. Thus, the first input circuit produces an internal signal having amplitude corresponding to the power supply voltage from the small amplitude signal. A second input circuit of the input/output interface receives the small amplitude signal in synchronous with the external clock signal and is composed of differential MOSFETs having a gate to which the small amplitude signal and a reference voltage having a level of a half of the small amplitude, an input section including a current source MOSFET connected to common sources of the differential MOSFETs and operating intermittently based on an internal clock signal taken in by the first input circuit, and a buffer circuit. The input section produces an internal signal having the amplitude corresponding to the power supply voltage from the small amplitude signal. The input section carries out a sampling operation to the internal signal in response to the internal clock signal. The buffer circuit holds the sampled signals.
Also, a source driver output circuit is disclosed in Japanese Laid Open Patent application (JP-A-Heisei 9-230829). In this reference, the source driver output circuit writes a pixel voltage to individual electrodes of liquid crystal elements of a TFT type liquid crystal display apparatus. In the source driver output circuit, a first N-channel FET inputs a display gradation voltage signal and a reference voltage signal and output a differential output of the display gradation voltage signal and the reference voltage signal. A first P-channel FET has a drain connected to the drain of the first N-channel FET, a source connected to a power supply line and a gate to which a constant voltage is biased to always turn on. A second N-channel FET has a drain connected to the drain of the first N-channel FET, a source connected to a ground line and has a current drive capability larger than the first N-channel FET. A second P-channel FET has a drain connected to the drain of the first N-channel FET, a source connected to the power supply line and has a current drive capability larger than the first P-channel FET. A control section connects the gate of the second N-channel FET to the output of a differential input stage to turn on the second N-channel FET when a common electrode is positive to the individual electrode, and turns off the second N-channel FET otherwise, and biases the gate of the second P-channel FET with a constant voltage to turn on the second P-channel FET when the common electrode is negative to the individual electrode, and turns off the second P-channel FET otherwise. Thus, the control section turns on the second N-channel FET and the second P-channel FET exclusively. A pixel voltage is outputted from a connection point to which the drains of the four FETs are connected.
Also, a semiconductor device and a data processing system are disclosed in Japanese Laid Open Patent application (JP-A-Heisei 11-273341). In this reference, a clock synchronous type semiconductor device is composed of a differential input buffer as an input interface circuit of an external signal and a latch circuit. The differential input buffer is composed of a differential input amplifier having a reference voltage as one of inputs and the external signal as the other, a first power switch transistor which supplies a higher power supply voltage to the differential input amplifier, and a second power switch transistor which supplies a lower power supply voltage to the differential input amplifier. A control circuit turns on the first and second power switch transistors in synchronous with a first state of the synchronous clock signal to activate the differential input buffer and to set the latch circuit to an input enable state, and turns off the first and second power switch transistors in synchronous with a second state of the synchronous clock signal to inactivate the differential input buffer and to set the latch circuit to a data latched state.